The present invention relates to solid-state electronic computer memories and in particular to a method and apparatus for anticipating age-related failure of transistor memory cells.
Solid-state electronic computer memories employ memory cells constructed of transistor elements that store at least two operating states associated with binary values of “one” and “zero”. Static random access memory (SRAM) employs a bi-stable latch circuit which holds its storage state indefinitely so long as power is applied. Dynamic random access memory (DRAM) stores its state in the form of a charge on capacitor. This charge slowly dissipates even when power is applied to the memory and must be “refreshed” periodically. Both forms of memory are “volatile” meaning that they lose their states when power is removed.
The transistors of both SRAM and DRAM change with age and such changes may ultimately lead to memory cell failure. Some types of memory cell failure may be detected using error correction codes (ECC) which provide for redundant memory bits and may be used to detect, after-the-fact, limited numbers of failures in a memory word comprised of multiple bits.
Logical gates are building block circuit elements of digital integrated circuits such as microprocessors. Logic gates implement a Boolean function using multiple transistors to receive an input at one or more inputs, interpret the inputs as logic levels, and provide an output voltage being the Boolean function of the inputs. Logical gates are normally combined to create more complex devices including counters, storage registers, and the like, the latter of which may be assembled into a processor or the like.
Like memory cells, logical gates are subject to age-related failure. After-the-fact detection of logical gate failure can be provided by redundant execution on two gate structures and comparing the outputs of the structures. Under the assumption that both structures will not fail simultaneously, this comparison will detect a wide variety of errors.
Co-pending U.S. application Ser. No. 14/012,255 entitled “Integrated Circuit Providing Fault Prediction” filed Aug. 28, 2013, assigned to the assignee of the present invention and hereby incorporated in its entirety by reference, provides a method of predicting failure of logical gates. This technique makes a comparison between the two similar circuit modules (for example, processor cores) where one is momentarily artificially aged. This aging process, for example, may be performed by lowering the operating voltage of one of the circuit modules to aggravate gate delay or by decreasing the “slack time”, that is, the time in excess of the guard band time normally allotted for state transition, to increase sensitivity to aging-induced gate delay. The outputs of the circuit modules are compared to predict failure in the aged circuit module. By using actual elements of the target circuit and by being able to predict further into the future through artificial aging, the likelihood of detecting infrequent errors caused by faults is increased, resulting in high accuracy. By rotating the aged circuit module through all circuit modules, good detection coverage may be obtained, and by employing a sampling with prediction the overhead of the redundancy is greatly reduced.
The above described failure prediction technique cannot be readily extended to memory circuits where redundant memory structures having the same data are normally not available for comparison and where the circuitry and/or time required to routing duplicate data to different memory structures would be prohibitive.